Miele T 9246 C Spécifications

UCD9246www.ti.comSLVSA34 –JANUARY 2010Digital PWM System Controller1FEATURESTool to Simulate, Configure, and MonitorPower Supply Performance2• Fully C

UCD9246SLVSA34 –JANUARY 2010www.ti.comPIN DESCRIPTIONSPIN NO. PIN NAME DESCRIPTION1 CS-4A Power stage 4A current sense input and input to analog compa

UCD9246www.ti.comSLVSA34 –JANUARY 2010PIN NO. PIN NAME DESCRIPTION47 BPCap 1.8V bypass capacitor connection48 AGND1 Analog Ground49 AGND2 Analog Groun

V3310 AmIBIASTo12-bit ADCResistortosetPMBusAddressADDR-0,ADDR-1pinsUCD9246UCD9246SLVSA34 –JANUARY 2010www.ti.comFUNCTIONAL OVERVIEWThe UCD9246 con

UCD9246www.ti.comSLVSA34 –JANUARY 2010Table 1. PMBus Address Bins (continued)RPMBusPMBus RESISTANCEPMBus ADDRESS(kΩ)6 1005 86.64 753 64.92 56.21 48.70

10 kWVinFCX491AUC9246ToPowerStage+3.3V+1.8V0.1 Fm4.7 FmV33FBV33AV33DBPCap0.1 FmUCD9246SLVSA34 –JANUARY 2010www.ti.comSome circuits in the device req

VrefDACVOUT_MARGIN_HIGHVOUT_CAL_OFFSETVOUT_MARGIN_LOWVOUT_COMMAND+LimiterVOUT_SCALE_LOOPOPERATIONCommandVOUT_MAX3:1MuxVrefDACCPUVEAVEAPVeadPMBusVEAN

+Vout-VoutR1R2EAPEANC2RinIoffP1RR =Kp2RR =1 K-UCD9246SLVSA34 –JANUARY 2010www.ti.comTable 3. Analog Front End ResolutionAFE_GAIN for EFFECTIVE EADC RE

EAOUTVK = VOUT_SCALE_LOOPV@2SW P1C =2 0.35 F R´ ´ ´p2 1 2EA O UT OFF SET1 2 1 21 2 1 2EA E AR R RV = V + IR R R RR + R + R + R +R Ræ ö æ öç ÷ ç ÷è ø è

UCD9246SLVSA34 –JANUARY 2010www.ti.comFigure 10. Digital CompensationThe nonlinear gain block allows a different gain to be applied to the system when

ClkresetPWMgatedriveoutputSysClkSyncInEADCtriggerSyncOutDPWMEngine(1of4)SwitchperiodCurrentbalanceadjCompensatoroutput(Calculateddutycycl

UCD9246SLVSA34 –JANUARY 2010www.ti.comThis integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be hand

swphase-phase spreadphasestt =NUCD9246SLVSA34 –JANUARY 2010www.ti.comThe PHASE_INFO PMBus command is also used to configure the number of power stages

rails IoutN TR = 0.45C( )tOC_thres CS_nom ImonV = V + V 1 e-D -tdetImon Imon OC_thres CS_nomT1R =C ln( V ) ln(ΔV V + V )D - -UCD9246www.ti.comSLVSA34

( )t/smoothed 1 2 1I (t) = I + (I I ) 1 e-- -t2 1lag2 limitI It = lnI Iæ ö-ç ÷-è øtUCD9246SLVSA34 –JANUARY 2010www.ti.comstage has the highest measure

UCD9246www.ti.comSLVSA34 –JANUARY 2010Input Voltage and Current MonitoringThe Vin/Iinpin on the UCD9246 monitors the input voltage and current. To mea

CD74HC4051VccA0 AGndA1A2A3A7A5A6A7S1S0ES2VeeTemp _1ATemp _1BTemp _2ATemp _2BTemp _3ATemp _4ATMUX-2TMUX-1TMUX-0Temperature+3.3 VUCD9246SLVSA34 –JANUARY

UCD9246www.ti.comSLVSA34 –JANUARY 2010Table 5. Temperature Sensor MappingTEMPERATURE MUX INPUT POWER STAGEA0 DPWM-1AA1 DPWM-1BA2 DPWM-3AA3 DPWM-2AA4 D

UCD9246SLVSA34 –JANUARY 2010www.ti.comWhen a voltage rail is in its idle state, the DPWM and SRE outputs are disabled, and the differential voltage on

UCD9246www.ti.comSLVSA34 –JANUARY 2010Method 1: Each rail has programmable delay times, TON_DELAY and TOFF_DELAY, before beginning a softstart ramp or

UCD9246SLVSA34 –JANUARY 2010www.ti.comEach rail can be optionally configured to monitor a sequencing input pin for a specified period of time after it

UCD9246www.ti.comSLVSA34 –JANUARY 2010Note that since the compensator and DPWM are digital, their transfer functions are known exactly and can bedivid

UCD9246www.ti.comSLVSA34 –JANUARY 2010ELECTRICAL CHARACTERISTICS (continued)PARAMETER TEST CONDITIONS MIN TYP MAX UNITERROR AMPLIFIER INPUTS EAPn, EAN

PACKAGE OPTION ADDENDUMwww.ti.com11-Apr-2013Addendum-Page 1PACKAGING INFORMATIONOrderable Device Status(1)Package Type PackageDrawingPins PackageQtyEc

TAPE AND REEL INFORMATION*All dimensions are nominalDevice PackageTypePackageDrawingPins SPQ ReelDiameter(mm)ReelWidthW1 (mm)A0(mm)B0(mm)K0(mm)P1(mm)W

*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)UCD9246RGCR VQFN RGC 64 2000 367.0 367.0 38.

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and otherch

UCD9246SLVSA34 –JANUARY 2010www.ti.comADC MONITORING INTERVALS AND RESPONSE TIMESThe ADC operates in a continuous conversion sequence that measures ea

UCD9246www.ti.comSLVSA34 –JANUARY 2010HARDWARE FAULT DETECTION LATENCYThe controller contains hardware fault detection circuits that are independent o

UCD9246SLVSA34 –JANUARY 2010www.ti.comFigure 1. I2C/SMBus/PMBus Timing in Extended Mode Diagram6 Submit Documentation Feedback Copyright © 2010, Texas

Compensator3P/3ZIIR12-bitADC260 kspsOscARM-7 corePMBusEAp4EAn4EAp3EAn3EAp2EAn2ADDR-0ADDR-1CS-1ACS-1BCS-2ACS-2BCS-3ACS-4AVin/IinVtrackTemperatureV33xx

UCD924616141513121132410987516333534363738464745394041424448433230312928271918202625242321172249515052535462636155565758606459CS-4ACS-3ACS-2AVin/ IinV

UCD7231 PowerStage-Vs+VsUCD7231RDLYVGGHS_SNSHS_GateILIMIOUTBP3VinAGNDCSPSRE_ModeCSNLS_GateSWSREFF BSTPWMPwPdPGNDVGG_DISVinVinTemperatureSensorTemp _1